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[Other Embeded program] ad714Xcontroller.tar

Description: AD714x to PC controller s firmware. Includes nice i2c driver, USART and fifo implementations for avr.
Platform: | Size: 25600 | Author: Dmitri | Hits:

[Com Port] UART16550

Description: UART控制器，集成FIFO，寄存器，数据位宽8位-UART controller, with FIFO, register, databus 8bits
Platform: | Size: 8192 | Author: huangluyang | Hits:

[Other] ethernet_tri_mode_latest.tar

Description: 10_100 0 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependance.To increase the flexibility,three optional modules can be added to or removed from the project. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.-10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependance.To increase the flexibility,three optional modules can be added to or removed from the project. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.
Platform: | Size: 3198976 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] SerMod

Description: 串口控制器，带双FIFO非常好控制 verilog-Serial controller, with pairs of FIFO very good control of verilog
Platform: | Size: 10240 | Author: zhangxinggang | Hits:

[FlashMX] flash

Description: FLASH控制器,利用FIFO记录好块地址 -FLASH controller
Platform: | Size: 5988352 | Author: wushi | Hits:

[VHDL-FPGA-Verilog] auto_w_r_spi

Description: 能够自动读写SPI ROM的控制器，读写的资料直接放到fifo中，经过实际的班子验证，很好用。-Can automatically read and write SPI ROM controller, read and write data directly into fifo, after the actual verification team, very good use.
Platform: | Size: 9216 | Author: wwww | Hits:

[VHDL-FPGA-Verilog] Keil

Description: USB大全第十八章实现slave FIFO的外部控制器程序-USB slave FIFO Daquan Chapter XVIII of the external controller to achieve program
Platform: | Size: 12288 | Author: 王学维 | Hits:

[VHDL-FPGA-Verilog] SJCJVC

Description: 初始化USB控制芯片，实现FIFO模式传输-Initialize the USB controller chip, the FIFO mode transfer
Platform: | Size: 1947648 | Author: CHEN HAO | Hits:

[VHDL-FPGA-Verilog] usb1_funct_latest.tar

Description: USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external micro-controller necessary. Derived from my USB 2.0 Function IP core, except all the high speed support logic has been ripped out and the interface was changed from shared memory to FIFO based. A basic test bench is now included as well. It should be viewed as a starting point to write a more comprehensive and complete test bench. I expect the users of this core to have some fundamental USB knowledge and be familiar with the UTMI specification and with the general USB transceivers (e.g. from philips). If you are not familiar with these two you should check out www.usb.org and read up on this subject ...
Platform: | Size: 59392 | Author: Andrey | Hits:

[ARM-PowerPC-ColdFire-MIPS] UART

Description: 用于S3C44B0X微控制器串口与外部设备的通信，可以设置缓冲区和FIFO两种方式 -Used for the the S3C44B0X micro-controller serial communication with external devices, you can set the buffer and FIFO two ways
Platform: | Size: 171008 | Author: yong | Hits:

[Other] AL422B-user-mannual

Description: The AL422 consists of 3M-bits of DRAM, and is configured as 393,216 words x 8 bit FIFO (first in first out). The interface is very user-friendly since all complicated DRAM operations are already managed by the internal DRAM controller. -The AL422 consists of 3M-bits of DRAM, and is configured as 393,216 words x 8 bit FIFO (first in first out). The interface is very user-friendly since all complicated DRAM operations are already managed by the internal DRAM controller.
Platform: | Size: 397312 | Author: liuguoyu | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: 文档介绍了SDRAM控制器，带有四个fifo,希望对初学者有一定的帮助。-The document describes the SDRAM controller with four fifo some help for beginners.
Platform: | Size: 19456 | Author: 夏建龙 | Hits:

[source in ebook] Chapter-9

Description: 9.1　异步FIFO设计实例　 9.2　DDR SDRAM Controller设计实例-9.1 Asynchronous FIFO design example 9.2 DDR SDRAM Controller Design Example
Platform: | Size: 3950592 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] FPGA-Source-Code_VHDL

Description: cypress fx2lp slave fifo fpga控制端源码-source code of FX2LP_SLAVE_FIFO CONTROLLER S
Platform: | Size: 1172480 | Author: 赵 | Hits:

[Other] SH6883

Description: The SH6883 is designed for high performance Low-speed USB devices. It contains an 8051 micro-controller, Low-Speed USB SIE, Transceiver and data FIFO, build-in 3.3V regulator, on-chip 8K bytes Mask ROM and internal 256 bytes data RAM, Time capture circuit, Base timer, programmable Watch-dog timer and Wake-up timer, 37 Selectable GPIO (on 48-pin LQFP package), support multiple type LED driving capability for different application, build-in internal 32KHz oscillator, POR and LVR circuit saving your external components cost
Platform: | Size: 2154879 | Author: simoon | Hits:
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